The signal is a unipolar Non Return to Zero (NRZ) with Additive White Gaussian Noise (AWGN) [2]. Firstly, the system is modelled in floating point format using Matlab [3]. Afterward, a design methodology is described for a Field Programmable Gate Array (FPGA) using fixed point format [4].The FPGA design is based on the System Generator from Xilinx [5]. Xilinx is one of the most important FPGA manufacturers, and System Generator is a design tool over Simulink of Matlab [6]. Simulink is a graphical environment Matlab design tool. In Simulink designs are described in the form of block diagrams and it has utilities for displaying and analysing the simulations. System Generator allows one to design in a fast and flexible way. It uses a low level of circuit details, so the simulations are fast, and the functionality of the system can be fully tested.

System Generator can be used to check the architecture and to analyse the effect of the number of bits on the system performance. Furthermore, it gives an approximate estimation of required hardware resources. Finally, physical performances are extracted with the Xilinx Integrated System Environment (ISE) [7].In this regard there have been several studies on ANN over FPGA for real time processing. Some of them focused on baseband signals, and are used as receptors [8] or as equalizers [9,10]. In the same way, others studies are for band pass signals [11]. The equalization can be performed to minimize distortion and noise introduced in the channel.

With modulated signals such systems can also be used for identifying the modulation type [12]; obviously, these studies are restricted to certain values of carrier frequencies and certain types of modulation. In multiuser communication ANNs are used to identify Anacetrapib and synchronize the channel or to make demodulation [13�C15]. Other studies have been developed on a very specific scenario [16]. In any case, few have been developed on FPGA [17], generally these studies use numerical floating point format on a personal computer. Many of these studies focus on the development of new architectures of ANNs [18] or new training methods [19].When the rate of the input signal increases the ANN implemented in a computer in floating point format cannot operate in real time. For decreasing the response time the ANN should be passed to a digital circuit, normally in fixed point format. The reason is that floating point arithmetic in a digital device needs a lot of hardware resources and power, without substantial improvement in speed. Besides, with the digital device the volume and the power consumption will decrease.One alternative is to use an Application Specific Integrated Circuit (ASIC).